(1) Field of the Invention
The present invention relates to a silicon field emission device. More particularly, it relates to a method for making an improved silicon field emission device to emit electrons at a little lower voltage by reducing the diameter of a gate aperture between a gate electrode and a silicon emitter to make the field emission structure sharp.
This field emission device may be utilized as an electron source in various display elements, light sources, amplifying devices, high speed switching devices, or sensors.
(2) Description of the Related Art
As a display monitor that can be substituted for a conventional cathode ray tube of a television, flat panel displays for wall television sets such as liquid crystal displays, plasma display panel, field emission device have received living study. The field emission device may have very high luminous efficiency and luminance by making unit pixed, i.e. the emitters per pixel high-integrated to 10.sup.4 -10.sup.5 tips/MM.sup.2, and is thought as a very suitable display for the embodiment of wall television sets.
Besides, even though silicon has a low electric conductivity and melting point, the applicability is gradually increased by the variety of the microfabrication technology that can facilitate fabrication of sharp emitter tips by means of silicon.
A representative embodiment of a structure of this silicon field emission device is depicted in FIG. 6. The reference numeral 60 designates a silicon substrate doped with impurities of high density to have a high conductivity. In a gate aperture 68 formed within insulating layers 62, 64 made on this substrate 60, an emitter 65 is formed to be united with the silicon substrate, serving as an electron emission part. And, a gate electrode 66 formed of molybdenum to enclose the emitter 65, with each space being of a predetermined width, is deposited on the insulating layer 64.
FIG. 8 depicts a perspective view of a conventional display using the electron emission device.
Referring to FIG. 8, there are formed a silicon substrate doped with impurities of high density and united with conic field emission emitters 65 in accordance with the direction of rows 81 and an insulating layer 64. In addition, a plurality of gate electrodes 66 is formed on the insulating layer 64 in accordance with the direction of columns 83. Gate apertures 68 are formed at a position corresponding to the gate electrodes 66 and the conic field emission emitters 65. On an upper substrate 90, a transparent conductive layer 92 and a fluorescent layer 94 are respectively deposited to be fixed to the upper substrate in a beta configuration. The lower substrate 60 and the upper substrate 90 form side members and an external part of a vacuum tube (not illustrated).
The operation of the display mentioned above is as follows.
Positive potential is applied to the transparent conductive layer 92. Responsive to a display signal, a predetermined potential difference is given between the silicon emitters 65 in the rows and the gate electrodes 66 in the columns. An appropriate electric field is produced between them such that electrons are emitted from the conic emitters 65. The electrons are emitted through the gate apertures 68 and collide with the fluorescent layer 94, and this fluorescent layer 94 radiates.
For example, by biasing the gate electrodes 66 within the range of several 10 V to several 100 V to the substrate 60, an electric field is produced between the conic tips of the emitters 65 having a microscopic diameter and the gate electrodes 66, and the electron emission of about several hundreds mA is achieved from the tips of the emitters 65.
In the field emission device for displaying a picture according to a display signal by the above operation, the gate aperture 68 is preferably small in diameter to improve the electron emission characteristics, i.e. to obtain the low voltage-driving condition.
When it comes to a real fabrication procedure, however, the insulating layer 64 and the gate electrodes 66 are deposited slantingly because of the limit to the deposition angle (under 90 degrees), and the gate aperture is apt to be enlarged in diameter. This occasions the increase of the gate voltage and difficulty in the low voltage-driving.
FIG. 7 depicts an enlarged sectional view of the step for depositing a gate prior to lift-off of an oxide mask and an oxide film underneath the oxide mask after the step for depositing the gate insulating layer 64 and the gate electrodes 66, in order to describe in detail the above problems. Since the gate electrode 66 and the insulating layer 64 are deposited slantingly according to a deposition angle .alpha., the oxide mask 63 is extended, and its profile is formed to be fan shaped under 10 degrees. Accordingly, this causes a side effect that the diameter of the gate aperture actually formed is more enlarged than the one in a design drawing.